In the manufacture of semiconductor memories defects are frequently encountered that afflict a limited number of memory elements in the memory matrix. The reason for the high probability of defects of this type resides in that in a semiconductor memory device the greatest part of the chip area is occupied by the memory matrix; moreover, it is in the memory matrix, and not in the peripheral circuitry, that the manufacturing process characteristics are usually pushed to limits.
In order to avoid that the presence of a limited number of defective memory elements, from among many millions, forces the rejection of the entire chip, and therefore decreases the manufacturing process yield, a number of "redundancy memory elements" are added to the chip. These additional memory elements are used as a replacement of those elements that, during testing of the memory device, prove defective. Selection circuits, with which the integrated component must necessarily be provided, and which allow the above-mentioned functional replacement of a defective memory element with a redundancy memory element, are indicated as a whole with the name of "redundancy circuitry." The set of redundancy memory elements and circuitry is defined for short as "redundancy".
The redundancy circuitry comprises programmable non-volatile memory registers suitable to store those address configurations corresponding to the defective memory elements; such registers are programmed once and for all during the memory device testing, and must retain the information stored therein even in absence of the power supply.
In practical implementations of redundancy, both rows ("word lines") and columns ("bit lines") of redundancy memory elements are provided in the memory matrix. Each redundancy word line or bit line is associated with a respective non-volatile memory register, wherein the address of a defective word line or bit line is stored so that, whenever the defective word line or bit line is addressed, the corresponding redundancy word line or bit line is selected. This implies that each non-volatile memory registers must be made up of a number of programmable memory cells at least equal to the number of bits in the row address bus, if the register is associated with a redundancy word line, or in the column address bus, if the register is instead associated with a redundancy bit line. Each memory cell of a memory register is therefore dedicated to store the logical state of a particular address bit, in the row or column address configurations, corresponding to a defective word line or bit line, and comprises at least one programmable memory element, a circuit for programming the memory element, a circuit for reading the information stored in the memory element and a circuit for comparing said information with the current logical state of the address bit associated with the memory cell.
If each non-volatile memory register is made up of a number of programmable memory cells exactly equal to the number of bits in the row address bus or in the column address bus, an ambiguous selection can take place. This ambiguity occurs because unprogrammed non-volatile memory registers, associated with unused redundancy word lines or bit lines, store that particular address configuration corresponding to the unprogrammed condition of the memory cells, and this particular address configuration belongs to the set of all the possible address configurations for the memory device. For example, when a non-defective word line or bit line is addressed whose address coincides with the logical configuration of the memory cells in an unprogrammed memory register, the redundancy word line or bit line associated with said unprogrammed register will be selected instead of the non-defective word line or bit line. The situation is even worse in memory devices where two or more redundancy word lines or bit lines are not used. In this case, the unprogrammed condition is the same for all the memory cells of the non-volatile memory registers, addressing the non-defective word line or bit line whose address coincides with the configuration of the unprogrammed memory cells would cause said two or more redundancy word lines or bit lines to be selected simultaneously.
To prevent such unacceptable ambiguous or even simultaneous selection, each non-volatile memory register is provided with an additional programmable memory cell (called "guard memory cell" or "control memory cell") which allows the selection of the associated redundancy word line or bit line only when the guard cell is programmed.
This causes a significant increase in the overall chip area.